`timescale 1ns / 1ps

module parity(clk,rstn,even_bit, odd_bit ,input_bus);
      output even_bit ;
      output reg odd_bit;
      input clk,rstn;
      input [11:0] input_bus;   
      always@(posedge clk or negedge rstn)
      if(!rstn) odd_bit<=1'b0; 
      else begin
        odd_bit =^ input_bus; 
      end
      assign even_bit = ~odd_bit;
endmodule

